Exemplary embodiments of the present invention relate to a technology for designing a semiconductor integrated circuit, and more particularly, to a duty cycle correction circuit (DCC) which corrects a duty cycle of a clock signal and outputs a clock signal with a corrected duty cycle.
In general, a semiconductor device including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) includes diverse internal circuits for diverse operations, and among the internal circuits is a duty cycle correction circuit (DCC) which receives a clock signal and corrects the duty cycle of the clock signal to be a desired duty cycle. The duty cycle correction circuit may receive an internal clock signal outputted from a Delay Locked Loop (DLL) and a Phase Locked Loop (PLL) that are included in the inside of a semiconductor device and correct the duty cycle of the internal clock signal to be 50%. That is, the pulsing duration of the internal clock signal becomes half the period of the internal clock signal (50:50). The corrected internal clock signal having a duty cycle of 50:50 becomes a basis for a stable circuit operation of the semiconductor device.
Meanwhile, a duty cycle correction circuit generally occupies a relatively large circuit area and has a complicated structure, thereby consuming significant current. Therefore, a duty cycle correction circuit with a simple structure is useful.